A post on habr.com documents an RP2040 driving an Intel High Definition Audio codec directly, with no chipset and no FPGA. HDA, also called Azalia, uses four wires and supports up to 15 channels in and 15 out, well past the two in, two out that I²S usually gives you.

The hard part is timing. BCLK must be exactly 24 MHz, and SYNC and SDO change on every edge, so 48 Mbit/s of double data rate output. Frames are 1,000 bits each, which works out to the 48 kHz base sample rate. The RP2040’s PIO blocks are used: one state machine for SDO, one for SYNC, one for SDI that also generates BCLK with a side-set, and a fourth that assigns the codec its bus address at startup.

Core 1 packs and unpacks samples, since the audio data is not aligned to 32-bit boundaries. The demo feeds all 10 DAC channels of an ALC889 with sine waves at 192 kHz. Overclocking the chip to a 32 MHz BCLK gave 256 kHz sampling, at which point the codec got hot.

See more at habr.com and content on GitHub.