TSU Protocol: An Open-Source RISC-V NPU Standard for Edge AI Inference

The Problem

AI inference is increasingly moving to the edge, but the hardware landscape is fragmented. Proprietary NPUs lock you into ecosystems. General-purpose CPUs burn too much power. Existing open-source hardware projects lack a coherent standard for AI-specific compute.

TSU Protocol is our answer: an open, royalty-free hardware standard built on RISC-V with 16 custom Agent-extended instructions, purpose-designed for LLM inference at the edge.

Architecture

TSU extends the RISC-V RV64 ISA with hardware instructions for:

MatMul & Attention — The core operations of transformer models, as single-cycle hardware ops

Softmax & RMSNorm — Normalization layers accelerated in silicon

SiLU & RoPE — Activation and positional encoding, offloaded from software

Agent Secure Enclave — Hardware-isolated execution environment for agent runtimes

Mesh Network — On-chip interconnect for multi-core scaling

Three Tiers

Tier Power Precision BOM…