This project implements a fully functional scientific calculator in hardware using an FPGA. It includes a custom soft CPU, microcode firmware, and supporting tools.

For the full story, see the blog .

Try it in a web browser:

Without debugger

With debugger

Project Structure

Folder Description

verilog/ SystemVerilog source files for the CPU, ALU, I/O, and test benches

ucode/ Microcode (firmware) for the soft CPU

quartus/ Quartus project files for FPGA synthesis

modelsim/ ModelSim simulation setup

Qt/ Qt-based simulator and debugger (uses Verilator)

calctest/ Command-line test harness for hardware verification (uses Verilator)

tools/ Assembler and script compiler for the microcode

Pathfinding/ Algorithm research and verification projects

Quick Start

The fastest way to try the calculator is to build the Qt simulator:

# From WSL2 cd /mnt/c/Projects/FPGA-Calculator/verilog make qt

Then open Qt/Calculator.pro in Qt Creator and build for "Desktop Qt MSVC2022 64 Bit".

See the verilog/ and Qt/…