TSU Protocol: Open-Source RISC-V NPUs for Edge AI

The Problem

Edge AI inference is dominated by proprietary hardware (Apple Neural Engine, Qualcomm Hexagon, Google TPU). There is no open-source alternative for running AI models on edge devices without vendor lock-in.

Our Solution: TSU Protocol

TSU Protocol is an anonymous, open-source hardware architecture standard for RISC-V-based Neural Processing Units (NPUs). We extend the RV64 ISA with 16 custom AI instructions for matrix multiply, convolution, activation functions, and pooling.

Three Tiers

Tier Power TOPS Target Node Target Price

TSU-1 5W 8 180nm $150

TSU-2 20W 40 28nm $300

TSU-3 45W 120 22nm/12nm $550

Current Status

✅ Architecture specification complete

✅ RTL design in progress (Verilog)

✅ FPGA validation pipeline designed

🔄 Seeking MPW tape-out sponsorship

Our Outreach Campaign

We've reached out to over 100+ tech companies across AI/ML frameworks, chip design, cloud infrastructure, and blockchain ecosystems.…